1. Field of the Invention
The present invention relates to electronic packages, used in a wide variety of applications, including, by way of example, packages that perform signal processing or signal conversions and complex timing control.
2. Description of the Related Art
An electronic package is a package which houses one or more integrated circuits (ICs). Electronic packages both protect ICs thereof by encasing the ICs in a protective resin and simplify handling of ICs. ICs perform various functions, which include, for example, processing data.
Currently, a common application of electronic packages is the routing of signals through electrical conductors. Due to advances in the sophistication and miniaturization of electronic devices, there is a demand to increase the number of input and output signals and decrease package size. As a consequence, the signal traces become smaller and the pitch of the traces, i.e., the distance separating the signals, becomes smaller. By having a smaller pitch, more signal traces can be included in a package. The manufacturability of such fine pitch circuitry is limited. Currently, the finest pitch circuitry is formed by chemical etching processes, which inherently place physical limitations on the ability to decrease the attainable pitch size and signal trace size to a desired level. Also, as the pitch and traces become smaller, parasitic effects arising from mutual capacitance and inductance become a serious hindrance to the operation speed of the packages.
The parasitic effects inherent from circuit layout patterns are typically accounted for in the design stage, during which many man-hours and much know-how must be dedicated to alter the patterns of the tracings. Often, the target speed of a package cannot be obtained at a desired size, and thus, a larger package size is required. Another approach for minimizing parasitic effects is to separate the signal traces from one plane to multiple planes, thereby alleviating the requirements on the size of the pitch and trace.
Additional problems associated with current electronic packages stem from the wire-bonding process, which is a fairly well known and accepted process in the industry. The wire-bonding process disadvantageously restricts the configuration of the input and output (I/0) pads on the die. For example, because gold wire contacts can short each other out, the I/O pads must typically line up precisely along the perimeter of the die. Further, compared to an area arrayed with I/O pads, the peripheral configuration of wire-bonded pads has a lower I/O density for a die greater than a certain critical size. Due to these restrictions, the flip chip process, which is capable of processing a die with an area array of I/O pads, has become increasingly important. However, successful practice of the flip-chip process requires significant capital re-investment and extensive training. Still another drawback is that current electronic packages communicate electrically. As a consequence, communications between such units impose tracing requirements on the PCB board. Such requirements also involve similar parasitic effects, and are cumbersome to implement. For example, a board containing 20 packages with each package having 300 I/Os that communicate with each other would require an extremely large number of circuit tracings.
Several proposals have been made to overcome these problems. For example, in U.S. Pat. No. 4,930,857 to Acarlar, an arrangement that accommodates electronic and optical components is disclosed. A multi-layer ceramic component sub-assembly provides an improved EMI and mechanical protection. A method to house different components is also disclosed. However, Arcarlar addresses only improved hermeticity. Other U.S. patents discuss methods to integrate optical circuitry and parts. For example, U.S. Pat. No. 5,249,245 to Lebby et al. discusses interconnecting optical electronic components, waveguides, and electronic components. U.S. Pat. Nos. 5,747,363 to Wei et al. and 5,821,571 to Lebby et al. disclose methods of integrating the electronic driver circuitry with an LED array or a dual-sided light emitting diode (LED and laser) with the driver circuitry. Other references discuss use of tapered surfaces to align optical waveguides to light-emitting surfaces and production of a monolithically integrated device consisting of the optical device and an electronic device.
However, none of the above-discussed techniques were intended for or proven to be successful in minimizing parasitic effects during communications within and between electronic packages. For example, U.S. Pat. No. 5,195,154 to Uchida discusses a technique to mount and align optical components on a board is disclosed. However, there is no discussion about using optical technology to alleviate parasitic effects.